ddsf:public:guidebook:06_append:glossary:r:risc
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ddsf:public:guidebook:06_append:glossary:r:risc [2020/07/09 01:52] nick |
ddsf:public:guidebook:06_append:glossary:r:risc [2021/07/15 12:22] (current) murphy ↷ Links adapted because of a move operation |
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| ===== Reduced Instruction Set Computer (RISC) ===== | ===== Reduced Instruction Set Computer (RISC) ===== | ||
| - | [[ddsf:private:cookbook:06_append:glossary| Return to Glossary ]] | + | [[ddsf:public:guidebook:06_append:glossary:start| Return to Glossary ]] |
| - | **Reduced Instruction Set Computer (RISC)** is a computer that uses a central processing unit (CPU) that implements the processor design principle of simplified instructions. To date, RISC is the most efficient CPU architecture technology. | + | **Reduced Instruction Set Computer (RISC)** is a computer that uses a [[ddsf:public:guidebook:06_append:glossary:c:cpu]] that implements the [[ddsf:public:guidebook:06_append:glossary:p:processor|processor]] design principle of simplified instructions. To date, RISC is the most efficient CPU architecture technology. |
| - | This architecture is an evolution and alternative to complex instruction set computing (CISC). With RISC, the basic concept is to have simple instructions that do less but execute very quickly to provide better performance. | + | This architecture is an evolution and alternative to [[ddsf:public:guidebook:06_append:glossary:c:cisc]]. With RISC, the basic concept is to have simple instructions that do less but execute very quickly to provide better [[ddsf:public:guidebook:06_append:glossary:p:performance|performance]]. |
| Source: [[https://www.techopedia.com/definition/2887/reduced-instruction-set-computer-risc | Reduced Instruction Set Computer (RISC) ]] | Source: [[https://www.techopedia.com/definition/2887/reduced-instruction-set-computer-risc | Reduced Instruction Set Computer (RISC) ]] | ||
ddsf/public/guidebook/06_append/glossary/r/risc.1594273938.txt.gz · Last modified: 2020/07/09 01:52 by nick
